(Phys.org) Computer scientists at Princeton University and physicists from Duke University collaborated to develop methods to design the next generation of quantum computers. Their study focused on QC systems built using trapped ion (TI) technology, which is one of the current front-running QC hardware technologies. By bringing together computer architecture techniques and device simulations, the team showed that co-designing near-term hardware with applications can potentially improve the reliability of TI systems by up to four orders of magnitude.
Their study was conducted as a part of the Software-Tailored Architecture for Quantum co-design (STAQ) project, an NSF funded collaborative research effort to build an trapped-ion quantum computer and the NSF CISE Expedition in Computing Enabling Practical-Scale Quantum Computing (EPiQC) project. It was published recently in the 2020 ACM/IEEE International Symposium on Computer Architecture.
To build the next generation of QCCD systems with 50 to 100 qubits, hardware designers have to tackle a variety of conflicting design choices. “How many ions should we place in each trap? What communication topologies work well for near-term QC applications? What are the best methods for implementing gates and shuttling operations in hardware? These are key design questions that our work seeks to answer,” said Prakash Murali, a graduate student at Princeton University.
Computer architecture and simulation-based design have been a key enabler of technology progress in classical computing. By leveraging these techniques for QC design and adopting a full system-view of the design space, rather than focusing on hardware alone, this study seeks to accelerate the progress towards the next major milestone of 50 to100 qubits.