(CambridgeNetwork) Cambridge-based Riverlane explains quantum computers will introduce a new computational paradigm for tackling problems beyond the reach of state-of-the-art classical high-performance computers (HPCs) in a newly published paper.
These devices will rely on classical components to supplement calculations. Optimising the delicate interplay between central processing units (CPUs) and quantum processing units (QPUs) will identify complex operational challenges that must be overcome to truly capture the benefits of quantum computing. Developing a hardware-conscious solution to these problems is one of the most pressing issues in near-term quantum computing.
Current quantum computers employ a `black-box’ model: quantum programs are written on a CPU and forwarded to the QPU to be implemented blindly. This model does not allow more intricate hardware-conscious programming to take place. Here we present three broad areas where this approach causes performance bottlenecks – an issue not often discussed within the quantum computing community:
Bandwith issues related to limited communication capacity between CPU and QPU;
Latency bottlenecks due to the round-trip time delay;
Build-up of qubit error rates due to short qubit coherence times.
Riverlane proposes a mitigating strategy that takes advantage of the classical hardware that is situated in close proximity to the QPU.